The present invention relates to a method of fabricating a non-volatile memory device, and more particularly to a method of fabricating a non-volatile memory device having a charge trapping layer.
Semiconductor memory devices used for storing data may be classified into volatile and non-volatile semiconductor memory devices. As power supply is stopped, volatile memory devices lose stored data, whereas non-volatile memory devices retain stored data. Accordingly, non-volatile memory devices are widely used when power cannot be continuously supplied or the use of low power is required as in portable telephone systems, memory cards for storing music and/or image data, and other appliances.
Cell transistors used in the non-volatile memory devices typically have a floating gate structure. The floating gate structure includes a gate insulating layer, a floating gate electrode, an insulating layer between gates, and a control gate electrode, which are sequentially stacked on a channel region of the cell transistor. However, severe interference phenomena are generated in the floating gate structure according to an increase in integration density. Accordingly, the floating gate structure poses a limit in increasing the integration density of the devices. Thus, recently, there is an increasing interest in a non-volatile memory device having a charge trapping layer in which interference phenomena are less generated as integration density increases.
The non-volatile memory device having a charge trapping layer generally has a structure in which a substrate having a channel region, a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode are sequentially stacked. As described above, the non-volatile memory device having a charge trapping layer can realize high integration density compared to the floating gate structure, but it has a drawback in that an erase operation speed is relatively low. The magnitude of a voltage applied to the control gate electrode in the erase operation should be increased to overcome the drawback. However, when a high voltage is applied to the control gate electrode in the erase operation, there may be a problem such as a backward tunneling phenomenon in which electrons in the control gate electrode pass through the blocking layer and enter into the charge trapping layer. Accordingly, a so-called Metal-Alumina-Nitride-Oxide-Silicon (MANOS) structure in which a high-k insulating layer such as an aluminum oxide (Al2O3) layer is used as a blocking layer and a metal gate having a sufficiently large work function is used as a control gate electrode has been recently proposed to suppress generation of the backward tunneling phenomenon.
In order to form a MANOS device, first, a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer are sequentially stacked on a substrate. The tunneling layer may be formed of an oxide layer. The charge trapping layer may be formed of a nitride layer. The blocking layer may be formed of an alumina layer. The control gate electrode layer may be formed of a metal layer. Then, an etching process using a hard mask layer pattern is performed to etch an exposed portion of the control gate electrode layer and also etch the exposed blocking layer. In this case, generally, excessive etching is performed to sufficiently etch the blocking layer. Accordingly, the charge trapping layer is also etched by a specified thickness through the excessive etching. Then, after the exposed charge trapping layer and tunneling layer are etched, the hard mask layer pattern is removed.
However, while the excessive etching is performed on the blocking layer, etching damage caused by ion bombardment may be generated on exposed sidewalls of the blocking layer, the charge trapping layer and an exposed surface of the charge trapping layer. Furthermore, a conductive polymer containing etching by-products such as aluminum (Al) or nitrogen (N) may be attached to the exposed sidewall of the blocking layer. In this case, undesirable trap sites may be formed at a portion with the etching damage. When electrons or holes are trapped in the trap sites, leakage current may be easily generated. Furthermore, the conductive polymer attached to the exposed sidewall of the blocking layer may form a charge moving path, and charges in the charge trapping layer may move to the control gate electrode through the charge moving path. Accordingly, threshold voltage distribution characteristics and/or retention characteristics of the device may be degraded.